MG7050HAN SAW-Based Differential Multi Output SAW OSCILLATOR (HCSL)
- Ultra Low jitter
0.3ps Max.2 or 4 outputs and it is able to reduce fan-out buffers
- Frequency range
100 MHz to 200 MHz
- Supply voltage
2.5V Typ / 3.3V Typ.
- External dimensions
7.0 × 5.0 × 1.6 mm
- Output
HCSL (2 or 4 outputs)
- Application
GbE, Fiber Channel, SAS, PCI express
Design Support Data Download
Specifications (characteristics)
Item | Symbol | Specifications | Conditions / Remarks | ||
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Output frequency range | f0 | 100 MHz to 200 MHz | Please contact us about available frequencies. | ||
100MHz , 125MHz , 156.25MHz , 200MHz | Standard frequency | ||||
Supply voltage | VCC | D : 2.5V ± 0.125V | C : 3.3V ± 0.33V | VCC1 and VCC2 need same voltage | |
Storage temperature | T_stg | -55°C to +125°C | Store as bare product after packing | ||
Operating temperature | T_use | A : 0°C to +70°C B : -20°C to +70°C D : -5°C to +85°C |
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Frequency tolerance *1 | f_tol | J : ± 50 × 10-6 L : ±100 × 10-6 |
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Current consumption | ICC | 55 mA Typ. 84 mA Max. |
60 mA Typ. 90 mA Max. |
2-outputs | OE = VCC with L_HCSL |
95 mA Typ. 128 mA Max. |
100 mA Typ. 136 mA Max. |
4-outputs | |||
Disable current | I_dis | 11 mA Typ. 23 mA Max. |
12 mA Typ. 25 mA Max. |
2-outputs | OE = GND |
15 mA Typ. 28 mA Max. |
16 mA Typ. 30 mA Max. |
4-outputs | |||
Symmetry | SYM | 45%to 55% | At outputs crossing point | ||
Output voltage | VOH | 0.66 V to 0.85 mV | DC characteristics | ||
VOL | -0.15 V to 0.15 V | ||||
Output load condition |
L_HCSL | 50Ω or 42.2Ω, with CL = 2pF, Rs = 33Ω or 27Ω |
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Input voltage | VIH | 70% VCC Min. | OE and ZSEL terminals | ||
VIL | 30% VCC Max. | ||||
Rise time / Fall time | Rr / Rf | 1 V/ns to 4 V/ns | Between -0.15 V and 0.15 V of differential output. | ||
Start-up time | t_str | 5 ms Typ., 10 ms Max. | Time at minimum supply voltage to be 0 s | ||
Phase Jitter | tPJ | 0.19 ps Typ. | 0.16 ps Typ. | f0 = 100MHz | Offset frequency: 12kHz to 20MHz |
0.18 ps Typ. | 0.15 ps Typ. | f0 = 125MHz | |||
0.16 ps Typ. | 0.13 ps Typ. | f0 = 156.25MHz | |||
0.14 ps Typ. | 0.12 ps Typ. | f0 = 200MHz | |||
0.3 ps Max. | |||||
Skew | t_skew | 20ps Typ. 50ps Max. | FSEL = H | ||
Aging | f_aging | N : ± 10 × 10-6 / year Max. | First year | +25°C, VCC = 2.5V , 3.3V |
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A : Included in Frequency tolerance *2 | 10 years |
*1 Frequency tolerance includes initial frequency tolerance, temperature variation, supply voltage change and reflow drift.
*2 "A" is not acceptable when Frequency tolerance is "J" and Operating temperature is "B" or "D".
Block diagram
ZSEL function
Output line
Differential Zo |
HCSL load L_HCSL |
Shunt resistor Rs |
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---|---|---|---|---|
ZSEL | H | 100 Ω | 50 Ω | 33 Ω |
L | 85 Ω | 42.2 Ω | 27 Ω |
External dimensions
(Unit :mm)
Footprint (Recommended)
(Unit :mm)
To maintain stable operation, provide a 0.01 µF to 0.1 µF by-pass capacitor at a location as near as possible to the power source terminal of the crystal product (between Vcc, Vcc1, Vcc2 - GND).