MG7050VAN SAW-Based Differential Multi Output OSCILLATOR(LVDS)
- Ultra Low jitter
0.3ps Max.2 or 4 outputs and it is able to reduce fan-out buffers
- Frequency range
100 MHz to 700 MHz
- Supply voltage
2.5V Typ. / 3.3V Typ.
- External dimensions
7.0 × 5.0 × 1.6 mm
- Output
LVDS (2 or 4 outputs)
- Application
Server, Storage, Network Instrument.
Design Support Data Download
Specifications (characteristics)
Item | Symbol | Specifications | Conditions / Remarks | ||
---|---|---|---|---|---|
Output frequency range | f0 | 100 MHz to 700 MHz | Please contact us about available frequencies. | ||
100MHz , 106.25MHz , 125MHz , 150MHz 156.25MHz , 200MHz , 212.5MHz , 250MHz 300MHz,312.5MHz |
Standard frequency | ||||
Supply voltage | VCC | D : 2.5V ± 0.125V | C : 3.3V ± 0.33V | VCC1 and VCC2 need same voltage | |
Storage temperature | T_stg | -55°C to +125°C | Store as bare product after packing | ||
Operating temperature | T_use | A : 0°C to +70°C B : -20°C to +70°C D : -5°C to +85°C |
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Frequency tolerance *1 | f_tol | J : ± 50 × 10-6 L : ±100 × 10-6 |
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Current consumption | ICC | 35mA Typ. 50mA Max. |
45mA Typ. 56mA Max. |
2-outputs | OE = VCC , L_LVDS = 100Ω |
40mA Typ. 66 mA Max. |
50mA Typ. 72 mA Max. |
4-outputs | |||
Disable current | I_dis | 7mA Typ. 18mA Max. |
8mA Typ. 20mA Max. |
OE = GND | |
Symmetry | SYM | 45% to 55% | At outputs crossing point | ||
Output voltage | VOH | 247 mV to 454 mV | DC characteristics | ||
VOL | 1.125 V to 1.375 V | ||||
Output load condition |
L_LVDS | 100 Ω | Connected between OUTnP and OUTnN | ||
Input voltage | VIH | 70% VCC Min. | OE and FSEL terminals | ||
VIL | 30% VCC Max. | ||||
Rise time / Fall time | tr / tf | 200 ps Typ., 400 ps Max. | Between 20% and 80% of differential output peak to peak voltage | ||
Start-up time | t_str | 5 ms Typ., 10 ms Max. | Time at minimum supply voltage to be 0 s | ||
Phase Jitter | tPJ | 0.19 ps Typ. | 0.16 ps Typ. | f0 = 100MHz | Offset frequency: 12kHz to 20MHz |
0.18 ps Typ. | 0.15 ps Typ. | f0 = 125MHz | |||
0.17 ps Typ. | 0.14 ps Typ. | f0 = 156.25MHz | |||
0.15 ps Typ. | 0.13 ps Typ. | f0 = 212.5MHz | |||
0.12 ps Typ. | 0.11 ps Typ. | f0 = 312.5MHz | |||
0.06 ps Typ. | 0.05 ps Typ. | f0 = 700MHz | |||
0.3 ps Max. | |||||
Skew | t_skew | 20ps Typ. 50ps Max. | FSEL = H | ||
Aging | f_aging | N:± 10 × 10-6 / year Max. | First year | +25°C, VCC = 2.5V , 3.3V |
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A: Included in Frequency tolerance *2 | 10 years |
*1 Frequency tolerance includes initial frequency tolerance, temperature variation, supply voltage change and reflow drift.
*2 "A" is not acceptable when Frequency tolerance is "J" and Operating temperature is "B" or "D".
Block diagram
FSEL function
2-outputs | OUT | OUT2 | |
---|---|---|---|
4-outputs | OUT1/OUT2 | OUT3/OUT4 | |
FSEL | H | f0 | f0 |
L | f0 | f0/2 |
External dimensions
(Unit :mm)
Footprint (Recommended)
(Unit :mm)
To maintain stable operation, provide a 0.01 µF to 0.1 µF by-pass capacitor at a location as near as possible to the power source terminal of the crystal product (between Vcc, Vcc1, Vcc2 - GND).