SG-210SDH (Crystal Oscillator Low-Jitter SPXO)

SG-210SxDSG-210SxH

RoHS Compliantpb free
  • Frequency range
    80.000MHz to 170.000MHz
    Fundamental mode oscillator
  • Supply voltage
    1.8V / 2.5V / 3.3V
  • Output
    CMOS
  • Function
    Standby(ST)
  • External dimensions
    2.5 × 2.0 × 0.8mm

Specifications

Item Symbol Specifications Condition/Remarks
SG-210SEH SG-210SDH SG-210SCH
Output frequency range f0 80.000MHz to 170.000MHz
100MHz, 106.25MHz, 125MHz,133.33MHz, 150MHz, 156.25MHz Standard
frequency. *1
Supply voltage VCC 1.8V ± 10% 2.5V ± 10% 3.3V ± 10% *2
Storage temperature T_stg -40°C to +125°C Store as
bare product.
Operating temperature T_use -40°C to +85°C
Frequency tolerance f_tol B: ±50 × 10-6, C: ±100 × 10-6 -20°C to +70°C
L: ±50 × 10-6, M: ±100 × 10-6 -40°C to +85°C
Current consumption ICC 6.0mA Max. 7.0mA Max. 9.0mA Max. No load condition,
80MHz ≤ f0 ≤ 125MHz
8.0mA Max. 9.0mA Max. 11.0mA Max. No load condition,
125MHz < f0 ≤ 170MHz
Stand-by current I_std 10.0μA Max. ST
Symmetry SYM 45% to 55% 50% VCC level,
L_CMOS ≤ 15pF
Output voltage VOH 90% VCC Min. IOH = -4mA
VOL 10% VCC Max. IOL = 4mA
Output load condition
(CMOS)
L_CMOS 15pF Max.  
Input voltage VIH 80% VCC Min. ST
VIL 20% VCC Max.
Rise time /Fall time tr / tf 3ns Max. 2ns Max. 20% VCC to
80% VCC level,
L_CMOS ≤15pF
Start-up time t_str 5ms Max. T=0 at 90% VCC
Jitter *3 tp-p 22ps Typ. 20ps Typ. Peak to Peak L_CMOS
≤ 15pF
Phase Jitter tPJ 0.7ps Max. 0.6ps Max. Offset frequency:
12kHz to 20MHz
Frequency aging f_aging ±5 × 10-6 / year Max. +25°C, First year

*1. Please contact us for inquiries regarding non-standard frequencies.
*2. f0 ≥ 157MHz: VCC ± 5%
*3. Based on SIA-3100C signal integrity analyzer made from WAVECREST.

Product name (Standard form)

External dimensions

dimension
(Unit: mm)


Note.
ST pin = HIGH or "open" : Specified frequency output.
ST pin = LOW : Output is high impedance, oscillation stops.

Footprint (Recommended)

footprint
(Unit: mm)


To maintain stable operation, provide a 0.01uF to 0.1uF by-pass capacitor at a location as near as possible to the power source terminal of the crystal product (between Vcc - GND).

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