SG-210SED (Crystal Oscillator Low Profile / High Stability SPXO)

SG-210SxDSG-210SxD

RoHS Compliantpb free
  • Frequency range
    50.000MHz to 80.000MHz
  • Supply voltage
    1.8V / 2.5V / 3.3V
  • Current consumption
    7.0mA Max.(SDD: 2.5V No load condition 80MHz)
  • Function
    Standby(ST)
  • External dimensions
    2.5 × 2.0 × 0.8mm

Specifications

Item Symbol Specifications Condition/
Remarks
SG-210SED SG-210SDD SG-210SCD
Output frequency range f0 50.000MHz to 80.000MHz
Supply voltage VCC 1.8V Typ.
1.6V to 2.2 V
2.5V Typ.
2.2V to 3.0 V
3.3V Typ.
2.7V to 3.6 V
Storage temperature T_stg -40°C to +125°C Store as bare product.
Operating temperature T_use -40°C to +85°C
Frequency tolerance f_tol B: ±50 × 10-6, C: ±100 × 10-6 -20°C to +70°C
L: ±50 × 10-6, M: ±100 × 10-6 -40°C to +85°C
Current consumption ICC 6.0mA Max. 7.0mA Max. 8.0mA Max. No load condition
Stand-by current I_std 10.0μA Max. ST
Symmetry SYM 45% to 55% 50% VCC level,
L_CMOS ≤ 30pF
Output voltage VOH VCC -0.4V Min. IOH=-8mA(SCD,SDD),
-4mA(SED)
VOL 0.4V Max. IOL= 8mA(SCD,SDD),
4mA(SED)
Output load condition
(CMOS)
L_CMOS 30pF Max.  
Input voltage VIH 70% VCC Min. ST
VIL 30% VCC Max.
Rise time / Fall time tr / tf 4ns Max. 20% VCC to 80% VCC level,
L_CMOS ≤ 30pF
Start-up time t_str 2ms Max. t=0 at 90% VCC
Jitter *1 tDJ 0.1ps Typ. 0.1ps Typ. Deterministic
Jitter
L_CMOS
≤ 15pF
tRJ 3.2ps Typ. 2.7ps Typ. Random
Jitter
tRMS 30ps Typ. 25ps Typ. Peak to
Peak
Phase Jitter tPJ 1.0ps Max. Offset
frequency:
12 kHz to
20 MHz
Frequency
aging
f_aging ±3 × 10-6/ year Max. +25°C,First year,
VCC= 1.8V,2.5V, 3.3V
±10 × 10-6/ 10 years Max. +25°C,10 years,
VCC= 1.8V,2.5V, 3.3V

*1 Based on DTS-2075 Digital timing system made from WAVECREST with jitter analysis software VISI6.

Product name (Standard form)

External dimensions

dimension
(Unit: mm)


Note.
ST pin = HIGH or "open" : Specified frequency output.
ST pin = LOW : Output is high impedance, oscillation stops.

Footprint (Recommended)

footprint
(Unit: mm)


To maintain stable operation, provide a 0.01uF to 0.1uF by-pass capacitor at a location as near as possible to the power source terminal of the crystal product (between Vcc - GND).

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