SG3225EAN/VAN SG5032EAN/VAN SG7050EAN/VAN

SG7050SG7050EAN/VAN
(7.0x5.0x1.4)
unit:mm

SG5032SG5032EAN/VAN
(5.0x3.2x1.0)

SG3225SG3225EAN/VAN
(3.2x2.5x1.05)

RoHS Compliant pb free pb free
  • Frequency range
    :73.5 MHz to 700 MHz
  • Supply voltage
    :2.5V / 3.3V
  • Function
    :Output enable (OE)
  • Output
    :LV-PECL or LVDS

DataSheetpdf(517KB)

Specifications

Item Symbol Specifications Condition/Remarks
LV-PECL LVDS
SG3225EAN
SG5032EAN
SG7050EAN
SG3225VAN
SG5032VAN
SG7050VAN
Output frequency range f0 73.5MHz to 700MHz Please contact us about available frequencies.
Supply voltage VCC K:2.5V to 3.3V VCC =±10%
Storage temperature T_stg -40°C to +125°C Store as bare product.
Operating temperature T_use B: -20°C to +70°C
G: -40°C to +85°C
Frequency tolerance f_tol C:±20 × 10-6
E:±30 × 10-6
J:±50 × 10-6
Current consumption ICC 65mA Max. 30mA Max. OE=Vcc, L_ECL=50Ω or L_LVDS=100Ω fo=700MHz
Disable current I_dis 20 mA Max. OE=GND
Symmetry SYM 45% to 55% At outputs crossing point
Output voltage
(LV-PECL)
VOH VCC-1.0 V to VCC-0.8 V - DC characteristics
dVOH VCC-1.78 V to VCC-1.62 V -
Output voltage
(LVDS)
VOs - 250mV to 450mV VOD1,,VOD2 DC characteristics
dVOs - 50mV Max. dVOD=VOD1,-VOD2
VOs - 1.15V to 1.35V VOD1,,VOD2
dVOs - 150mV Max. dVOD=VOD1,-VOD2
Output load condition (ECL)/(LVDS) L_ECL 50Ω - Terminated to VCC -2.0 V
L_LVDS - 100Ω Connected between OUT to
Input voltage VIH 70% VCC Min. OE terminal
VIL 30% VCC Max.
Rise time / Fall time tr/tf 350 ps Max. 300 ps Max. Between 20 % and 80 % of (VOH-VOL).
Between 20 % and 80 %of Differential Output peak to peak
voltage.
Start-up time t_str 3ms Max. Time at minimum supply voltage to be 0s
Phase Jitter tPJ 0.6 ps Max.*1 Offset frequency: 12 kHz to 20 MHz
Frequency aging f_aging ±5 × 10-6 / year Max. +25°C, VCC=2.5V or 3.3V,
First year.

*1. f0=243MHz to250MHz, 486MHz to 500MHz are 0.9ps Max.

ProductName(Standardform)

External dimensions

 

dimension(Unit: mm)

Footprint (Recommended)

 

footprint(Unit: mm)

To maintain stable operation, provide a 0.01uF to 0.1uF by-pass capacitor at a location as near as possible to the power source terminal of the crystal product (between Vcc - GND).