For customers using AD951x series, AD952x series Clock Cleaner Applications from Analog Devices

(AD951xSeries: AD9510, AD9512, AD9513, AD9514, AD9515, AD9516-0,1,2,3,4, AD9517-0,1,2,3,4)

(AD952xSeries: AD9520-0,1,2,3,4,5, AD9522-0,1,2,3,4,5, AD9523, AD9523-1, AD9524, AD9525, AD9528)


Customers can find the suitable VCXO products and features ADI clock cleaners require.

Clock Solution for ClockCleaner AD951x, AD952x series from Analog Devices

There are two major factors VCXO products imply.

VCXO Features
Output CMOS
 Lower frequency (1M~170MHz) Easy connection with IC circuitry, but vulnerable from external noise.Larger high frequency harmonic component than LV-PECL.
LV-PECL Higher frequency (50M~800MHz) Stable data transfer is available with impedance matching and complicated circuitry to IC input port.
Smaller high frequency harmonic component than CMOS Epson VCXO has HFF(High Frequency Fundamental) and it makes low noise design with fundamental oscillation. Epson recommends LV-PECL for low noise design.
APR
Absolute Pull Range
Lower APR (±50ppm) Lower noise, narrow frequency pull-ability.
Higher APR (±100ppm) Higher noise, wide frequency pull-ability Customer can choose APR for system design.
Customer can choose APR for system design.

Epson VCXO line up.

Output Size
[mm] 		Frequency
[ MHz ]		 Products
CMOS 2.5x2.0x0.7t 30.72
61.44		 VG2520CAN
5.0x3.2x1.2t 1~81 VG-4231CB
7.0x5.0x1.4t 1~60
60~80
80~170		 VG-4231CA,
VG-4232CA,
VG-4501CA,
VG-4502CA
LV-PECL 5.0x3.2x1.3t 100~500 VG-4513CB
7.0x5.0x1.6t VG-4513CA

Simulation libraries

ADIsimcLK is a clock cleaner simulator supported by Analog Devices ADI. ADIsimCLK can simulate ADI clock cleaners' PLL clock features with combination of Epson VCXOs. Epson provides VCXOs'simulation libraries for ADIsimCLK.

VCXO Products

Product Output Frequency
 Absolute pull range
VG-4513CA/CB LV-PECL 100 ~ 491MHz ±50ppm, ±100ppm
VG-4231CE/CB CMOS 25 ~ 61.44MHz ±100ppm

ADIsimCLK is registered Trade Mark of Analog Devices, Inc.
Customers can refer to Analog Devices about ADIsimCLK.
ADIsimCLK Down load
http://www.analog.com/en/design-center/advanced-selection-and-design-tools/interactive-design-tools/adisimclk.html

(Link to Analog Devices,Ink. HP)

<Quick start for ADIsimCLK>

  1. Down load Epson Library from this WEB site to your PC.
    2. library data:(epson1_01.zip:11kb)
  2. Install Epson Library to your PC correct drive.
    The directory for install Epson Library file
    C:…\ADIsimCLKVer1.6\LibBackup\VCO\epson.lib
    3. simulator
  3. Start ADIsimCLK and select Epson VCXO Library for simulation.
    simulator

Please follow instructions below when ADIsimCLK application software fails to recognize Epson.lib.

  1. Stop ADIsimCLK application software.
  2. Erase the files Epson.lib, Epson.sfm and other files have name of Epson from the directory.
  3. Install Epson. Lib into the directory again.
  4. Take the customer's ownership of the file (Epson.lib).
    Refer to (Link to Microsoft page) http://technet.microsoft.com/en-us/library/cc753659.
  5. Start ADIsimCLK application software again.

Simulation and measurement sample
(Analog Devices AD9523-1 and Epson VG-4513)

ADIsimCLK Simulation result and comparison with measured data.
Clock Cleaner : AD9523-1
VCXO:VG-4513CA 122.8MHz,245.76MHz

Loop Filter constants setting

lcp 9.0uA    
Cpole1 1500pF internal fixed
Rzero 135kΩ internal  
Cext 0.33uF external default
Rpole2 165kΩ internal fixed
Cpole2 337pF internal fixed

VCXO setting (Noise, Kv of VCXO)

PLL1 simulation result 1

VCXO frequency VG-4513CA 122MHz VG-4513CA 245MHz
KV 53.2Hz 70.5Hz
LOOP BW 135kΩ internal
Phase Margin 80.4degrees 79.5degrees
Zero 3.57Hz 3.57Hz
Pole 615Hz 615Hz
Last Pole 3.68kHz 3.68kHz

PLL2 simulation result 2

simulation

PLL2 simulation result 1 (Parameter)

OUT1:
Frequency: 122.880MHz
Broadband Jitter (>1kHz)= 215fs rms
SNR = 77.40dB ENOB = 12.90bits
at IF Freq = 100MHz
Integrated Phase Noise from 12.0kHz to 20.0MHz
Timing Jitter = 144fs rms
Phase Jitter EVM = 0.01 %rms
Phase Jitter = 0.006 degrees rms
ACI / ACR = -82.1dBc
Delay from Ref to OUT1 is 0s

PLL2 simulation result 2 (Noise)

simulation

The comparison result (simulation vs. measured data)

VCXO Simulation Measured value
VG-4513CA 122.88MHz LVPECL 144fsec 146.7fsec
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